The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, field effect transistors (FETs) such as fin field effect transistors (FinFETs) have been developed for their high drive currents with small footprints compared to traditional planar FETs. In one method, FinFETs are formed on bulk substrate for reduced manufacturing cost. However, typical bulk FinFETs suffer a punch-through issue where leakage currents may flow in a region not controlled by a gate. To overcome the punch-through issue, conventional methods implant dopant impurities into regions between the fin channel and the bulk substrate. Thermal treatments in subsequent process steps may cause diffusion of the implanted dopant impurities. These methods unavoidably introduce dopant impurities into the whole fin, adversely reducing the carrier mobility thereof. In addition, dopant impurity implantation may also adversely affect channel strain of the fin. Therefore, although conventional punch-through mitigating methods have been generally adequate for their intended purposes, they are not satisfactory in all respects.